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as4c 32m16sm confidential 1 | p a g e r e v 1 . 0 , j u l y 2014 512m (32m x 16) bit synchronous dram (sdram) confidential preliminary (rev. 1.0, july / 2014) revision history AS4C32M16SM revision details date rev 1.0 preliminary datasheet ju l y 201 4
as4c 32m16sm confidential 2 | p a g e r e v 1 . 0 , j u l y 2014 512m (32m x 16) bit synchronous dram (sdram) co nfidential preliminary (rev. 1.0, july /2014) features ? pc133 - compliant ? configurations C 32 meg x 16 (8 meg x 16 x 4 banks) ? fully synchronous; all signals registered on positive edge of system clock ? internal, pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes concurrent auto precharge and auto refr esh modes ? self refresh mode ? auto refresh C 64ms, 8192 - cycle refresh (commercial and industrial) ? lvttl - compatible inputs and outputs ? single 3.3v 0.3v power supply ? operating temperature range o commercial (0?c to +70?c) o industrial ( C 40?c to +85?c) ? timing C cycle time o 7.5ns @ cl = 3 (pc133) o 7.5ns @ cl = 2 (pc133) ? plastic package C ocpl2 o 54 - pin tsop ii (400 mil) pb - free ? all parts rohs compliant table 1. key timing parameters clock frequency set up time hold time access time cl =3 t rcd (ns) t rp (ns) 133 mhz 1.5ns 0.8ns 5.4ns 13.75 13.75 cl = cas (read) latency table 2 C ordering information product part no org temperature package as4c 32m16sm - 7tcn 32 m x 16 commercial 0c to 70 c 54 - pin tso p ii (400mil) as4c 32m16sm - 7tin 32 m x 16 industrial - 40c to 8 5c 54 - pin tsop ii (400mil) table 3 C address table parameter 32m x 16 configuration 8 meg x 16 x 4 banks refresh count 8k row addressing 8k a [12:0] bank addressing 4 ba [1:0] column addressing 1k a [9:0]
as4c 32m16sm confidential 3 | p a g e r e v 1 . 0 , j u l y 2014 general description the 512mb sdram is a high - speed cmos, dynam ic random - access memory contain ing 536,870,912 bits. it is internally configured as a quad - bank dram with a synchro nous interface (all signals are registered on the po sitive edge of the clock signal, clk).each of the x4s 134,217,728 - bit banks is organized as 8192 rows by 4096 columns by 4bits. each of the x8s 134,217,728 - bit banks is organized as 8192 rows by 2048 columns by 8 bits. each of the x16s 134,217,728 - bit b anks is org anized as 8192 rows by 1024 col umns by 16 bits. read and write accesses to the sdram are burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programme d se quence. accesses begin with the r egistration of an ac tive command, which is then fol lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba[1:0] select the bank; a[12:0] select the row). the ad dress bits registered coincident with the read or write command are used to select the starting column location for the burst access. the sdram provides for programmable read or write burst lengths (bl) of 1, 2, 4, or 8locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self - timed row precharge that is initiated at the end of the burst sequence. the 512mb sdram uses an internal pipelined architecture to achieve hi gh - speed oper ation. this arch itecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high - speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and pr ovide seamless, high - speed, ran dom - access operation. the 512mb sdram is designed to operate in 3.3v memory systems. an auto refresh mode is provided, along with a power - saving, power - down mode. all inputs and out - puts are lvttl - compatible. sdrams offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column - address generation, the ability to interleave between internal banks to hide pr echarge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
as4c 32m16sm confidential 4 | p a g e r e v 1 . 0 , j u l y 2014 functional block diagrams
as4c 32m16sm confidential 5 | p a g e r e v 1 . 0 , j u l y 2014 pin and ball assignments and descriptions figure 4: 54 - pin tsop (top view) notes: 1. the # symbol indicates that the signal is active low 2. package may or may not be assembled with a location notch.
as4c 32m16sm confidential 6 | p a g e r e v 1 . 0 , j u l y 2014 table 4: pin and ball descriptions symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sa mpled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power - down an d self refresh operation (all banks idle), active power - down (row active in any bank), or clock suspend operation (burst/access in pro gress). cke is synchronous except after the device enters power - down and self - refresh modes, where cke becomes asynchronou s until after exiting the s ame mode. the input buffers, in cluding clk, are disabled during power - down and self - refresh modes, providing low stand by power. cke may be tied high. cs# input chip select: cs# enables (registered low) and disables (reg istered high) the command decod er. all commands are masked when cs# is registered high, but read/write bursts already in progress will continue, and dqm operation will retain its dq mask capability while cs# is high. cs# provides for external bank selection on sys tems with multiple banks. cs# is considered part of the command code. cas#, ras#,we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. x16:dqml, dqmhldqm, udqm(54 - ball) input input/output mask: dqm is an input m ask signal for write ac cesses and an output enable sig nal for read accesses. input data is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high - z state (two - clock latency) when dqm is sampled high during a read cycl e. on the x4 and x8, dqml (pin 15) is a nc and dqmh is dqm. on the x16, dqml corresponds to dq[7:0], and dqmh corresponds to dq[15:8]. dqml and dqmh are considered same state when referenced as dqm. ba[1:0] input bank address input(s): ba[1:0] defines to which bank the active, read, write, or precharge command is being applied. a[12:0] input address inputs: a[12:0] are sampled during the active command (row address a[12:0]) and read or write command (column address a[9:0], a11, and a12 for x4; a[9:0] and a11 for x8;a[9:0] for x16; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by a10 (low). the address inputs also provide the op - code during a load mode register command. x16:dq[15:0] i/o data input/output: data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51 are nc for x8; and pins 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are nc for x4). vddq supply dq power: dq power to the die for improved noise immunity. vssq supply dq ground: dq ground to the die for improved noise immunity. vdd supply power supply: +3.3v 0.3v. vss supply ground. nc - these should be left unco nnected.
as4c 32m16sm confidential 7 | p a g e r e v 1 . 0 , j u l y 2014 package dimensions figure 5: 54 - pin plastic tso p (400 mil) C package codes t
as4c 32m16sm confidential 8 | p a g e r e v 1 . 0 , j u l y 2014 temperature and thermal impedance it is imperative that the sdram devices temperature specifications, shown in table 6(page 14), be maintained to en sure the junction temp erature is in the proper operat ing range to meet data sheet specifications. an importa nt step in maintaining the prop er junction temperature is using the devices thermal impedances correctly. the ther mal impedances are listed in tabl e 6 (page 14) for the applicable die revision and packages being made available. these thermal impedance values vary according to the density, package, and particular design used for each device. incorrectly using thermal impedances can produce significa nt errors. to ensure the compatibility of curre nt and future de - signs, contact alliance memory applications engineering to confirm thermal impedance values. the sdram devices safe junction temperature range can be maintained when the tc specification is not exceeded. in applications where the devices ambient temperature is too high, use of forced air and/or heat sinks may be r equired to satisfy the case tem perature specifications. table 5: temperature limits parameter symbol min max unit notes opera ting case temperature commercial tc 0 80 c 1,2,3,4 industrial - 40 90 junction temperature commercial t j 0 85 c 3 industrial - 40 95 ambient temperature commercial t ? 0 70 c 3,5 industrial - 40 85 peak reflow temperature t peak - 260 c notes: 1. max operating case temperature, tc, is measured in the center of the package on the top side of the device, as shown in figure 6 (page 14). 2. device functionality is not guaranteed if the device exceeds maximum tc during opera tion. 3. all temperature specifications must be satisfied. 4. the case temperature should be measured by gluing a thermocouple to the top - center of the component. this should be done with a 1mm bead of conductive epoxy, as de - fined by the jedec eia/jesd51 standards. take care to ensure that the thermocouple bead is touching the case. 5. operating ambient temperature surrounding the package.
as4c 32m16sm confidential 9 | p a g e r e v 1 . 0 , j u l y 2014 table 6: thermal impedance simulated values ja (c/w) ja (c/w) ja (c/w) airflow = airflow = airflow = die revision package substrate 0m/s 1m/s 2m/s jb (c/w) jc (c/w) rev d 54 - pin tsop 2 - layer 62.6 48.4 44.2 19.2 6.7 4 - layer 39.2 32.3 30.6 19.3 notes: 1. f or designs expected to last beyond the die revision listed, contact alliance memory applications engineering to confirm thermal impedance values. 2. thermal resistance data is sampled from multiple lots, and the values should be view ed as typical. 3. these are estimates; actual results may vary. figure 6: example: temperature test point location, 54 - pin tsop (top view) 22.22mm 11.11mm test point 10.16mm 5.08mm note: 1. package may or may not be assembled with a locat ion notch.
as4c 32m16sm confidential 10 | p a g e r e v 1 . 0 , j u l y 2014 electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in th e operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 7: absolute maximum ratings voltage/temperature symbol min max unit notes voltage on v dd /v ddq supply relative to v ss v dd /v ddq C 1 +4.6 v 1 voltage on inputs, nc, or i/o balls relative to v ss v in C 1 +4.6 storage temperature (plastic) t stg C 55 +155 c power dissipation C C 1 w note: 1. v dd and v ddq must be within 300mv of each other at all times. v ddq must not exceed v dd . table 8: dc electrical characteristics and operating conditions notes 1 C 3 apply to all parameters and conditions; v dd /v ddq = +3.3v 0.3v parameter/condition symbol min max unit notes supply voltag e v dd , v ddq 3 3.6 v input high voltage: logic 1; all inputs v ih 2 v dd + 0.3 v 4 input low voltage: logic 0; all inputs v il C 0.3 +0.8 v 4 output high voltage: i out = C 4ma v oh 2.4 C v output low voltage: i out = 4ma v ol C 0.4 v input leakage curr ent: i l C 5 5 a any input 0v v in v dd (all other balls not under test = 0v) output leakage current: dq are disabled; 0v v out v ddq i oz C 5 C 5 a operating temperature: commercial t a 0 +70 ?c industrial t a C 40 +85 ?c notes: 1. all voltages reference d to v ss . 2. the minimum specifications are used only to indicate c ycle time at which proper opera tion over the full temperature range is ensured; (0c ta +70c (commercial), C 40c ta +85c (industrial), and C 40c ta +105c (automotive)). 3. an init ial pause of 100 s is required after power - up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v ddq must be powered up simultaneously. v ss and v ssq must be at same potential.) the two auto refresh command wake - ups should be repeated any time the t r ef refresh requirement is excee ded. 4. v i h overshoot: v i h , max = v ddq + 2v for a pulse width 3ns, and the pulse width cannot be greater than one - third of the cycle rate. v il undershoot: v i l , min = C 2v for a pulse width 3n s.
as4c 32m16sm confidential 11 | p a g e r e v 1 . 0 , j u l y 2014 table 9: capacitance note 1 applies to all parameters and conditions notes: 1. this parameter is sampled. v dd , v ddq = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 2. pc100 specifies a maximum of 4pf. 3. pc100 specifies a maximum of 5pf. 4. pc100 specifies a maximum of 6.5pf. 5. pc133 specifies a minimum of 2.5pf. 6. pc133 specifies a minimum of 2.5pf. 7. pc133 specifies a minimum of 3.0pf.
as4c 32m16sm confidential 12 | p a g e r e v 1 . 0 , j u l y 2014 electrical specifications C i dd parameters table 10: i dd specifications and conditions ( - 7 ) notes 1 C 5 apply to all parameters and conditions; v dd /v ddq = +3.3v 0.3v notes: 1. all voltages referenced to v ss . 2. the minimum specifications are used only to indicate cycle t ime at which proper operation over the full temperature range is ensured; (0c ta +70c (commercial), C 40c ta +85c (industrial), and C 40c ta +105c (automotive)). 3. an initial pause of 100 s is required after power - up, followed by two auto r efresh commands, before proper device operation is ensured. (v dd and v ddq must be powered up simultaneously. v ss and v ssq must be at same potential.) the two auto refresh command wake - ups should be repeated any time the t ref refresh requirement is exceeded . 4. ac operating and i dd test conditions have v il = 0v and v ih = 3.0v using a measurement reference level of 1.5v. if the input transition time is longer than 1ns, then the timing is measured from v il, max and v ih , min and no longer from the 1.5v midpoint. clk should always be 1.5v referenced to crossover. 5. i dd specifications are tested after the device is properly initialized. 6. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 7. enables on - chip refresh and address counters. 8. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 9. the i dd current will increase or decrease proportionally according to the amoun t of frequency alteration for the test condition. 10. address transitions average one transition every two clocks. 11. pc100 specifies a maximum of 4pf. 12. pc100 specifies a maximum of 5pf. 13. for - 7 , cl = 3 and tck = 7.5ns , cl = 2 and tck = 7.5ns. 14. cke is high during refresh command period t rfc (min) else cke is low. the i dd6 limit is actually a nominal value and does not result in a fail value. parameter/condition max symbol - 7 unit notes operating current: active mode; burst = 2; read or write; t rc = t rc i dd1 110 ma 6, 9, 10 , (min) 13 standby current: power - down mode; all banks idle; cke = low i dd2 3.5 ma 13 standby current: active mode; cke = high; cs# = high; all banks active i dd3 45 ma 6, 8, 10 , after t rcd met; no accesses in progress 13 operating current: burst mode; page burst; read or write; all banks ac tive i dd4 115 ma 6, 9, 10 , 13 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd5 255 ma 6, 8, 9, 10 , t rfc = 7.813 s i dd6 6 ma 13, 1 4 self refresh current: cke 0.2v standard i dd7 6 ma low power (l) i dd7 3 ma 7
AS4C32M16SM confidential 13 | p a g e r e v 1 . 0 , j u l y 2014 electrical specifications C ac operating conditions table 11: electrical characteristics and recommended a c operat ing conditions ( - 7 ) notes 1, 2, 4, 5, 7, and 20 apply to all parameters and conditions - 7 parameter symbol min max unit notes access time from clk (positive edge) cl = 3 t ac(3) C 5.4 ns 18 cl = 2 t ac(2) C 6 address hold time t ah 0.8 C ns address setup time t as 1.5 C ns clk high - level width t ch 2.5 C ns clk low - level width t cl 2.5 C ns clock cycle time cl = 3 t ck(3) 7.5 C ns 14 cl = 2 t ck(2) 10 C cke hold time t ckh 0.8 C ns cke setup time t cks 1.5 C ns 21 cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 C ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 C ns data - in hold time t dh 0.8 C ns data - in setup time t ds 1.5 C ns data - out high - z time cl = 3 t hz(3) C 5.4 ns 6 cl = 2 t hz(2) C 6 ns data - out low - z time t lz 1 C ns data - out hold time (load) t oh 2.7 C ns data - out hold time (no load) t oh n 1.8 C ns 19 active - to - precharge command t ras 44 120,000 ns active - to - active command period t rc 66 C ns 23 active - to - read or write delay t rcd 20 C ns refresh period (8192 rows) t ref C 64 ms auto refresh period t rfc 66 C ns precharge command period t rp 20 C ns active bank a to active bank b command t rrd 15 C t ck transition time t t 0.3 1.2 ns 3 write recovery time t wr 1 clk + C ns 15 7.5ns 15 C 16 exit self refresh - to - active command t xsr 75 C ns 12
AS4C32M16SM confidential 14 | p a g e r e v 1 . 0 , j u l y 2014 table 12: ac f unctional characteristics ( - 7 ) notes 1 C 5 and note 7 apply to all parameters and conditions notes: 1. the minimum specifications are used only to indicate cycle time a t which proper operation over the full temperature range (0?c t a +70?c commercial temperature, - 40?c t a +85?c industrial temperature, and - 40?c t a +105?c automotive temperature) is ensured. 2. an initial pause of 100 s is required after power - up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v ddq must be powered up simultaneously. v ss and v ssq must be at same potential.) the two auto refresh command wake - ups should be repeated any time the t r ef refresh r equirement is excee ded. 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equiva lent load: q 50pf 6. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high - z. 7. ac operating and i dd test conditions have v il = 0v and v ih = 3.0v using a measurement reference level of 1.5v. if the input transition time is longer than 1ns, then the timing is measured from v il , max and v ih , min and no longer from the 1.5v midpoint. clk should al - ways be 1.5v r eferenced to crossov er. 8. timing is specified by t cks. clock(s) specified as a reference only at minimum cycle rate. 9. timing is specified by t wr plus t rp. clock(s) specified as a reference only at minimum cycle rate. 10. timing is specified by t wr. 11. required clocks are specif ied by jedec functionality a nd are not dependent on any tim ing parameter. 12. clk must be toggled a minimum of two times during this period. 13. based on t ck = 7.5ns for - 7 14. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including twr, and precharge commands). cke may be used to reduce the data rate . parameter symbol - 7 unit notes las t data - in to burst stop command t bdl 1 t ck 11 read/write command to read/write command t ccd 1 t ck 11 last data - in to new read/write command t cdl 1 t ck 11 cke to clock disable or power - down entry mode t cked 1 t ck 8 data - in to active command t dal 5 t ck 9, 1 3 data - in to precharge command t dpl 2 t ck 10, 1 3 dqm to input data delay t dqd 0 t ck 11 dqm to data mask during writes t dqm 0 t ck 1 1 dqm to data high - z during reads t dqz 2 t ck 11 write command to input data delay t dwd 0 t ck 11 load mode register command to active or refresh command t mrd 2 t ck 17 cke to clock enable or power - down exit setup mode t ped 1 t ck 8 last data - in to pre charge command t rdl 2 t ck 10, 1 3 data - out high - z from precharge command cl = 3 t roh(3) 3 t ck 11 cl = 2 t roh(2) 2 t ck 11
AS4C32M16SM confidential 15 | p a g e r e v 1 . 0 , j u l y 2014 15. auto precharge mode only. the precharge timing budget ( t rp) begins at 7ns for C cl2 and 7.5ns for - 7 cl3 after the first clock delay and after the last write is executed. 16. precharge mode only. 17. jedec and pc100 specify three clocks. 18. t ac for - 75/ - 7e at cl = 3 with no load is 4.6ns and is guaranteed by design 19. parameter guarant eed by design. 20. pc100 specifies a maximum of 6.5pf. 21. for operating frequencies 45 mhz, t cks = 3.0ns. 22. auto precharge mode only. the precharge timing budget ( t rp) begins 6ns for - 6a after the first clock delay, after the last write is executed. may not ex ceed limit set for pre - charge mode. 23. dram devices should be evenly addressed when being accessed. disproportionate accesses to a particular row address may result in reduction of the product lifetime.
AS4C32M16SM confidential 16 | p a g e r e v 1 . 0 , j u l y 2014 functional description in general, 512mb sdram de vices (32 meg x 4 x 4 banks ) are quad - bank dram that operate at 3.3v and include a synchronous interface. all signals are registered on the positive edge of the clock signal, clk. each of the x16s 134,217,728 - bit banks is org anized as 8192 rows by 1024 co l umns by 16 bits. read and write accesses to the sdram are burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, followe d by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank; a [ 12:0] select the row). the address bits (x4: a [ 9:0], a11, a12 ; x8: a [ 9:0], a1 1 ; x16: a [ 9:0] ) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections pro - vide detailed information cove ring device initialization, register definition, command descriptions, and device operation.
AS4C32M16SM confidential 17 | p a g e r e v 1 . 0 , j u l y 2014 commands the following table provides a quick reference of available commands, followed by a written description of each command. additional truth tables (table 14 (page 28), ta ble 15 (page 30), and table 16 (page 32)) provide current state/next state information. table 13: truth table C commands and dqm operation note 1 applies to all parameters and conditions name (function) cs# ras# cas# we# dqm addr dq notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 2 read (select bank and column, and start read burst) l h l h l/h bank/col x 3 write (select bank and column, and start write burst) l h l l l/h bank/col valid 3 burst terminate l h h l x x active 4 precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or self refresh (enter self refresh mode) l l l h x x x 6, 7 load mode register l l l l x op - code x 8 wri te enable/output enable x x x x l x active 9 write inhibit/output high - z x x x x h x high - z 9 notes: 1. cke is high for all commands shown except self refresh. 2. a[0 :n ] provide row address (where a n is the most significant address bi t), ba0 and ba1 determine which bank is made active. 3. a[0 :i ] provide column address (where i = the most significant column address for a given device configuration). a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the a uto precharge feature. ba0 and ba1 determine which bank is being read from or written to. 4. the purpose of the burst terminate command is to stop a data burst, thus the command could coincide with data on the bus. however, the dq column reads a dont care state to illustrate that the burst terminate command can occur when there is no data present. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks pre - charged and ba0, ba1 are dont care. 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. a[11:0] define the op - code written to the mode register. 9. activates or deactivates the dq during writes (zero - clo ck delay) and reads (two - clock delay). command inhibit the command inhibit function prevents new commands from being executed by the device, regardless of whether the clk signal is enabled. the device is effectively de - selected. operations already in pr ogress are not affected.
AS4C32M16SM confidential 18 | p a g e r e v 1 . 0 , j u l y 2014 no operation (nop) the no operation (nop) command is used to perform a nop to the selected device (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress ar e not affected. load mode register (lmr) the mode registers are loaded via inputs a[ n:0] (where a n is the most significant ad - dress term), ba0, and ba1(see mode register (page 35)). the load mode register command can only be i ssued when all banks are idle and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to activate a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided selects the row. this row remains active for accesses until a precharge command is is - sued to that bank. a precharge command must be issued before opening a different row in the same bank. figure 7: active command
AS4C32M16SM confidential 19 | p a g e r e v 1 . 0 , j u l y 2014 read the rea d command is used to initiate a burst read access to an active row. the values on the ba0 and ba1 inputs select the bank; the address provided selects the starting column location. the value on input a10 determines whether auto precharge is used. if au - to precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. read data appears on the dq subject to the logic level on the dqm inputs two clocks e arlier. if a given dqm signal was registered high, the corresponding dq will be high - z two clocks later; if the dqm signal was registered low, the dq will provide valid data. figure 8: read command
AS4C32M16SM confidential 20 | p a g e r e v 1 . 0 , j u l y 2014 write the write command is used to initiate a burst write access to an active row. the values on the ba0 and ba1 inputs select the bank; the address provided selects the starting column location. the value on input a10 determines whether auto precharge is used. if au - to precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dq is written to the memory array, subject to the dqm in - put logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data is written to memory; if the dqm signal is registered high, the corresponding data inputs are ignored and a write is not executed to that byte/column location. figure 9: writ e command
AS4C32M16SM confidential 21 | p a g e r e v 1 . 0 , j u l y 2014 precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issu ed. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is precharged, inputs ba0 and ba1 select the bank. otherwise ba0 and ba1 are treated as dont care. after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands are issued to that bank. figure 10: precharge command burst terminate the burst terminate command is used to truncate either fixed - length or continuous page bursts. the most recentl y registered read or write command prior to the burst terminate command is truncated.
AS4C32M16SM confidential 22 | p a g e r e v 1 . 0 , j u l y 2014 refresh auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas# - before - ras# (cbr) refresh in conventional drams. this command is non - persistent , so it must be issued each time a refresh is required. all active banks must be pre - charged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge com mand, as shown in bank/row activation (page 40). the addressing is generated by the internal refresh controller. this makes the address bits a dont care during an auto refresh command. regardless of device width, the 512mb s dram requires 8192 auto refresh cycles every 64ms (commercial and industrial). providing a distributed auto refresh command every 7.813 s (commercial and industrial) will meet the refresh requirement and ensure that each row is refreshed. alternatively, 81 92 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms (commercial and industrial). self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered - down . when in the self - refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). after the self refresh command is registered, all the inputs to the sdram b ecome a dont care with the exception of cke, which must remain low. after self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self re - fresh mode for a m inimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defined as a signal cycling within tim ing constraints specified for the clock pin) prior to cke going back high. after cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of any internal refresh in progress. upon exiting the self - refresh mode, auto refresh commands must be issued at the specified intervals, as both self refresh and auto refresh utilize the row refresh counter.
AS4C32M16SM confidential 23 | p a g e r e v 1 . 0 , j u l y 2014 truth tables table 14: truth table C current state bank n , command to bank n notes 1 C 6 apply to all parameters and conditions current state cs# ras# cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select and activate row) l l l h auto refresh 7 l l l l load mode register 7 l l h l precharge 8 row active l h l h read (select column and start read burst) 9 l h l l write (select co lumn and start write burst) 9 l l h l precharge (deactivate row in bank or banks) 10 read l h l h read (select column and start new read burst) 9 (auto precharge disabled) l h l l write (select column and start write burst ) 9 l l h l precharge (truncate read burst, start precharge) 10 l h h l burst terminate 11 write l h l h read (select column and start read burst) 9 (auto precharge disabled) l h l l write (select colu mn and start new write burst) 9 l l h l precharge (truncate write burst, start precharge) 10 l h h l burst terminate 11 notes: 1. this table applies when cke n - 1 was high and cke n is high (see table 16 (page 32)) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank - specific, except where noted (for example, the current state is for a specific bank and the commands shown can be issued to that bank wh en in that state). exceptions are covered below. 3. current state definitions: idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register acc esses are in progress. read : a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write : a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been termina ted. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or supported commands to the other bank should be issued on any clock edge occurring during these states. supported commands to any o ther bank are determined by the banks current state and the conditions described in this and the following table. precharging : starts with registration of a precharge command and ends when t rp is met. after t rp is met, the bank will be in the idle state . row activating : starts with registration of an active command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state.
AS4C32M16SM confidential 24 | p a g e r e v 1 . 0 , j u l y 2014 read with auto precharge enabled : starts with registration of a read command with auto precharge enab led and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto precharge enabled : starts with registration of a write command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing : starts with registration of an auto refresh command and ends when t rfc is met. after t rfc is met, the device will be in the all banks idle state. accessing mode register : starts with registration of a load mode register command and ends when t mrd has been met. after t mrd is met, the device will be in the all banks idle state. precharging all : starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank spec ific; requires that all banks are idle. 8. does not affect the state of the bank and acts as a nop to that bank. 9. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharg e disabled. 10. may or may not be bank specific; if all banks need to be precharged, each must be in a valid state for precharging. 11. not bank - specific; burst terminate affects the most recent read or write burst, regardless of bank.
AS4C32M16SM confidential 25 | p a g e r e v 1 . 0 , j u l y 2014 table 15: truth tabl e C current state bank n, command to bank m notes 1 C 6 apply to all parameters and conditions current state cs# ras# cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation ( nop/continue previous operation) idle x x x x any command otherwise supported for bank m row activating, active, or l l h h active (select and activate row) precharging l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read l l h h active (select and activate row) (auto precharge disabled) l h l h read (select column and start new read burst) 7, 1 0 l h l l write (select column and start write burst) 7, 1 1 l l h l precharge 9 write l l h h active (select and activate row) (auto precharge disabl ed) l h l h read (select column and start read burst) 7, 1 2 l h l l write (select column and start new write burst) 7, 1 3 l l h l precharge 9 read l l h h active (select and activate row) (with auto precharge) l h l h read (select column and start new read burst) 7, 8, 1 4 l h l l write (select column and start write burst) 7, 8, 1 5 l l h l precharge 9 write l l h h active (select and activate row) (with auto precharge) l h l h read (select column and start read burst) 7, 8, 1 6 l h l l write (select column and start new write burst) 7, 8, 1 7 l l h l precharge 9 notes: 1. this table applies when cke n - 1 was high and cke n is high (table 16 (page 32)), and a fter t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; for example, the cur - rent state is for bank n and the commands shown can be issued to bank m , assuming that bank m is in su ch a state that the given command is supported. exceptions are covered below. 3. current state definitions: idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts /accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write : a write burst has been initiated, with auto precharge disabled, and has not y et terminated or been terminated.
AS4C32M16SM confidential 26 | p a g e r e v 1 . 0 , j u l y 2014 read with auto precharge enabled : starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto precharge e nabled : starts with registration of a write command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh, and load mode r egister commands can only be is sued when all b anks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes to bank m listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m burst. 9. the burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or without auto pre - charge), the read to bank m will interrupt the read on bank n , cas latency (cl) later. 11. for a read without auto precharge interrupted by a w rite (with or without auto pre - charge), the write to bank m will interrupt the read on bank n when registered. dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (wi th or without auto pre - charge), the read to bank m will interrupt the write on bank n when registered, with the data - out appearing cl later. the last valid write to bank n will be data - in registered one clock prior to the read to bank m . 13. for a write with out auto precharge interrupted by a write (with or without auto pre - charge), the write to bank m will interrupt the write on bank n when registered. the last valid write to bank n will be data - in registered one clock prior to the read to bank m . 14. for a re ad with auto precharge interrupted by a read (with or without auto pre - charge), the read to bank m will interrupt the read on bank n , cl later. the pre - charge to bank n will begin when the read to bank m is registered. 15. for a read with auto precharge inte rrupted by a write (with or without auto pre - charge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the wri te to bank m is registered. 16. for a write with auto precharge interrupted by a read (with or without auto pre - charge), the read to bank m will interrupt the write on bank n when registered, with the data - out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data - in registered one clock prior to the read to bank m . 17. for a write with auto precharge interrupted by a write (with or without auto pr e - charge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one cloc k to the write to bank m .
AS4C32M16SM confidential 27 | p a g e r e v 1 . 0 , j u l y 2014 table 16: truth table C cke notes 1 C 4 apply to all parameters and conditions current state cke n - 1 cke n command n action n notes power - down l l x maintain power - down self refresh x maintain self refresh clo ck suspend x maintain clock suspend power - down l h command inhibit or nop exit power - down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 all banks idle h l command inhib it or nop power - down entry all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see table 15 (page 30). notes: 1. cke n is the logic state of cke at clock edge n; cke n - 1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power - down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in t he all banks idle state after t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during the t xsr period. 7. after exiting clock suspend at clock e dge n , the device will resume operation and recognize the next command at clock edge n + 1.
AS4C32M16SM confidential 28 | p a g e r e v 1 . 0 , j u l y 2014 initialization sdram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera tion. after power is applied to v dd and v ddq (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified f or the clock pin), the sdram re quires a 100 s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100 s period and continuing at least through the end of this period, command inhibit or nop commands must be applied. after the 100 s delay has been satisfied with at least one command inhi bit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, at least two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. if desired, the two auto refresh commands can be issued after the lmr command. the recommended power - up sequence for sdram: 1. simultaneously apply power to v dd and v ddq . 2. assert and hold cke at a lvttl logic low since all inputs and outputs are lvttl - compatible. 3. provide stable clock signal. stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. wait at least 100 s prior to issuing any comm and other than a command inhib it or nop. 5. starting at some point during this 100 s period, bring cke high. continuing at least through the end of this period, 1 or more command inhibit or nop commands must be applied. 6. perform a precharge all command. 7. wait at least t rp time; during this time nops or deselect commands must be given. all banks will complete their precharge, thereby placing the device in the all banks idle state. 8. issue an auto refresh command. 9. wait at least t rf c time, during which only nops or command inhibit commands are allowed. 10. issue an auto refresh command. 11. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 12. the sdram is now ready for mode register programming. becau se the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. using the lmr command, program the mode register. the mode register is programmed via the mode register set comma nd with ba1 = 0, ba0 = 0 and retains the stored information until it is programmed again or the device loses power. not programming the mode register upon initialization will result in default settings which may not be desired. out - puts are guaranteed high - z after the lmr command is issued. outputs should be high - z already before the lmr command is issued. 13. wait at least t mrd time, during which only nop or deselect commands are al - lowed. at this point the dram is ready for any valid command.
AS4C32M16SM confidential 29 | p a g e r e v 1 . 0 , j u l y 2014 note: mor e than two auto refresh commands can be issued in the sequence. after steps 9 and 10 are complete, repeat them until the desired number of auto refresh + t rfc loops is achieved. figure 11: initialize and load mode register notes: 1. the mode register ma y be loaded prior to the auto refresh cycles if desired. 2. if cs is high at clock high time, all commands applied are nop. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high - z after command is issued. 5. a12 should be a low at t p + 1.
AS4C32M16SM confidential 30 | p a g e r e v 1 . 0 , j u l y 2014 m ode register the mode register defines the specific mode of operation, including burst length (bl), burst type, cas latency (cl), operating mode, and write burst mode. the mode register is programmed via the load mode register command and retains the stor ed information until it is programmed again or the device loses power. mode register bits m[2:0] specify the bl; m3 specifies the type of burst; m[6:4] specify the cl; m7 and m8 specify the operating mode; m9 specifies the write burst mode; and m10 C m n sho uld be set to zero to ensure compatibility with future revisions. m n + 1 and m n + 2 should be set to zero to select the mode register. the mode registers must be loaded when all banks are idle, and the controller must wait t mrd before initiating the subse quent operation. violating either of these requirements will result in unspecified operation.
AS4C32M16SM confidential 31 | p a g e r e v 1 . 0 , j u l y 2014
AS4C32M16SM confidential 32 | p a g e r e v 1 . 0 , j u l y 2014 burst length read and write accesses to the device are burst oriented, and the burst length (bl) is programmable. the burst length determines the maximum num ber of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, 8, or continuous locations are available for both the sequential and the interleaved burst types, and a continuous page burst is available for the seq uential type. the continuous page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block when a boundary is reached. the block is uniquely sele cted by a[8:1] when bl = 2, a[8:2] when bl = 4, and a[8:3] when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. continuous page bursts wrap within the page when the boundary is reache d. burst type accesses within a given burst can be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address.
AS4C32M16SM confidential 33 | p a g e r e v 1 . 0 , j u l y 2014 table 17: burst definition table order of accesses within a burst burst length starting column address type = sequential type = interleaved 2 a0 0 0 - 1 0 - 1 1 1 - 0 1 - 0 4 a1 a0 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 a2 a1 a0 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 continuous n = a0 C an/9/8 (location 0 C y) cn, cn + 1, cn + 2, cn + 3...cn - 1, not supported cn... notes: 1. for full - page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16). 2. for bl = 2, a1 C a9, a11 (x4); a1 C a9 (x8); or a1 C a8 (x16) select the block - of - two burst; a0 selects the starting column within the block. 3. for bl = 4, a2 C a9, a11 (x4); a2 C a9 (x8); or a2 C a8 (x16) select the block - of - four burst; a0 C a1 select the starting column within the block. 4. for bl = 8, a3 C a9, a11 (x4); a3 C a9 (x8); or a3 C a8 (x16) select the block - of - eight burst; a0 C a2 select the starting column within the block. 5. for a full - page burst, the full row is selected and a0 C a9, a11 (x4); a0 C a9 (x8); or a0 C a8 (x16) select the starti ng column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. for bl = 1, a0 C a9, a11 (x4); a0 C a9 (x8); or a0 C a8 (x16) select the unique column to be accessed, and mode register bit m3 is ignored.
AS4C32M16SM confidential 34 | p a g e r e v 1 . 0 , j u l y 2014 cas latency the cas latency (cl) is the delay, in clock cycles, between the registration of a read command and the availability of the output data. the latency can be set to two or three clocks. if a read command is registered at clock ed ge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data is valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dq start driving after t1 and the data is valid by t2. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 13: cas latency operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are r eserved for future use. reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m[2:0] applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single - location ( non - burst ) accesses.
AS4C32M16SM confidential 35 | p a g e r e v 1 . 0 , j u l y 2014 bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened. this i s accomplished via the active command, which selects both the bank and the row to be activated. after a row is opened with the active command, a read or write command can be issued to that row, subject to the t rcd specification. t rcd (min) should be divid ed by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) result s in 2.5 clocks, rounded to 3. this is reflected in figure 14 (page 40), which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been precharged. the minimum time interval between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row - access overhead. the mini - mum time interval between successive active commands to different banks is defined by t rrd. figure 14: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck < 3
AS4C32M16SM confidential 36 | p a g e r e v 1 . 0 , j u l y 2014 read operation read bursts are initiated with a read command, as shown in figure 8 (page 24). the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. in the following figures, auto precharge is disabled. during read bursts, the valid data - out element from the starting column address is available following the cas latency after the read command. each subsequent data - out element will be va lid by the next positive clock edge. figure 16 (page 43) shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other commands have been initiated, the dq signals will go to high - z. a continuous page burst continues until terminated. at the end of the page, it wraps to column 0 and continues. data from any read burst can be truncated with a subsequent read command, and data from a fixed - length read burst can be followed immediately b y data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncat ed. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 16 (page 43) for cl2 and cl3. sdram devices use a pipelined arc hitecture and therefore do not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a read command. full - speed random read accesses can be performed to the same bank, or each subsequent r ead can be performed to a different bank.
AS4C32M16SM confidential 37 | p a g e r e v 1 . 0 , j u l y 2014 figure 15: consecutive read bursts
AS4C32M16SM confidential 38 | p a g e r e v 1 . 0 , j u l y 2014 figure 16: random read accesses data from any read burst can be truncated with a subsequent write command, and data from a fixed - length read burst can be followed imme diately by data from a write command (subject to bus turnaround limitations). the write burst can be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there is a possibility that the device driving the input data will go low - z before the dq go high - z. in this case, at least a single - cycle delay should occur between the last read data and the write command. the dqm input is use d to avoid i/o contention, as shown in figure 17 (page 44) and figure 18 (page 45). the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress da - ta - out from the read. after the write command is registered, the dq will go to high - z (or remain high - z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command th at truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4, then the writes at t5 and t7 would be valid, and the write at t6 would be invalid.
AS4C32M16SM confidential 39 | p a g e r e v 1 . 0 , j u l y 2014 the dqm signal must be de - asserted prior to the wr ite command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 1 7 (page 44) shows where, due to the clock cycle frequency, bus contention is avoided w ithout having to add a nop cycle, while figure 18 (page 45) shows the case where an additional nop cycle is required. a fixed - length read burst may be followed by or truncated with a precharge command to the same bank, provided that auto precharge was not activated. the pre - charge command should be issued x cycles before the clock edge at which the last de - sired data element is valid, where x = cl - 1. this is shown in figure 19 (page 45) for each pos sible cl; data element n + 3 is either the last of a burst of four or the last de - sired data element of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row prec harge time is hidden during the access of the last data element(s). in the case of a fixed - length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from th e same fixed - length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate fixed - length or continuous page bursts. figure 17: read - to - write
AS4C32M16SM confidential 40 | p a g e r e v 1 . 0 , j u l y 2014 figure 18: read - to - write with extra clock cycle figure 19: read - to - precharge continuous - page read bursts can be truncated with a burst terminate command and fixed - length read bursts can be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 20 (page 46) for each possible cas latency; data element n + 3 is the last desired data element of a longer burst.
AS4C32M16SM confidential 41 | p a g e r e v 1 . 0 , j u l y 2014 figure 20: terminating a read burst
AS4C32M16SM confidential 42 | p a g e r e v 1 . 0 , j u l y 2014 figure 21: alternating bank read accesses
AS4C32M16SM confidential 43 | p a g e r e v 1 . 0 , j u l y 2014 figure 22: read continuous page burst
AS4C32M16SM confidential 44 | p a g e r e v 1 . 0 , j u l y 2014 figure 23: read C dqm operation
AS4C32M16SM confidential 45 | p a g e r e v 1 . 0 , j u l y 2014 write operation write bursts are initiated with a write command, as shown in figure 9 (page 25). the starting column and bank ad dresses are provided with the write command and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the foll owing figures, auto precharge is disabled. during write bursts, the first valid data - in element is registered coincident with the write command. subsequent data elements are registered on each successive positive clock edge. upon completion of a fixed - len gth burst, assuming no other commands have been initiated, the dq will remain at high - z and any additional input data will be ignored (see figure 24 (page 50)). a continuous page burst continues until terminated; at the end of t he page, it wraps to column 0 and continues. data for any write burst can be truncated with a subsequent write command, and data for a fixed - length write burst can be followed immediately by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command (see figure 25 (page 51)). data n + 1 is either the last of a burst of two or the last desired dat a element of a longer burst. sdram devices use a pipelined architecture and therefore do not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full - speed ra ndom write accesses within a page can be performed to the same bank, as shown in figure 26 (page 52), or each subsequent write can be performed to a different bank. figure 24: write burst
AS4C32M16SM confidential 46 | p a g e r e v 1 . 0 , j u l y 2014 figure 25: write - to - write d ata for any write burst can be truncated with a subsequent read command, and data for a fixed - length write burst can be followed immediately by a read command. after the read command is registered, data input is ignored and writes will not be executed (see figure 27 (page 52)). data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. data for a fixed - length write burst can be followed by or truncated with a pre - charge command to the sam e bank, provided that auto precharge was not activated. a continuous - page write burst can be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element i s registered. the auto precharge mode re - quires a t wr of at least one clock with time to complete, regardless of frequency. in addition, when truncating a write burst at high clock frequencies ( t ck < 15ns), the dqm signal must be used to mask input data f or the clock edge prior to and the clock edge coincident with the precharge command (see figure 28 (page 53)). data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. following the pre charge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed - length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed - length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge c ommand is that it can be used to truncate fixed - length bursts or continuous page bursts.
AS4C32M16SM confidential 47 | p a g e r e v 1 . 0 , j u l y 2014 figure 26: random write cycles figure 27: write - to - read
AS4C32M16SM confidential 48 | p a g e r e v 1 . 0 , j u l y 2014 figure 28: write - to - precharge fixed - length write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command is ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate c ommand. this is shown in figure 29 (page 54), where data n is the last desired data element of a longer burst.
AS4C32M16SM confidential 49 | p a g e r e v 1 . 0 , j u l y 2014 figure 29: terminating a write burst
AS4C32M16SM confidential 50 | p a g e r e v 1 . 0 , j u l y 2014 figure 30: alternating bank write accesses
AS4C32M16SM confidential 51 | p a g e r e v 1 . 0 , j u l y 2014 figure 31: write C co ntinuous page burst
AS4C32M16SM confidential 52 | p a g e r e v 1 . 0 , j u l y 2014 figure 32: write C dqm operation burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a 1. in this mode, all write commands result in the acce ss of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0).
AS4C32M16SM confidential 53 | p a g e r e v 1 . 0 , j u l y 2014 precharge operation the prec harge command (see figure 10 (page 26)) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a sub - sequent row access some specified time ( t rp) after the prechar ge command is is - sued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged (a10 = low), inputs ba0 and ba1 select the bank. when all banks are to be precharged (a10 = high), inputs ba0 and ba1 are treated as dont care. after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature that performs the same individ ual - bank precharge function described previously, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the continuous page burst mode where auto precharge does not apply. in the specific case of write burst mode set to single location access with burst le ngth set to continuous, the burst length setting is the overriding setting and auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that t he precharge is initiated at the earliest valid stage within a burst. another command cannot be issued to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was is - sued at the earliest possible time, as described for each burst type in the burst typ e (page 37) section. alliance memory sdram supports concurrent auto precharge; cases of concurrent auto pre - charge for reads and writes are def ined below. read with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will interrupt a read on bank n following the programmed cas latency. the precharge to bank n begins when the read to bank m is registered (see fig ure 33 (page 59)). read with auto precharge interrupted by a write (with or without auto precharge) a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the pre - charge to bank n begins when the write to bank m is registered (see figure 3 4 (page 60)). write with auto precharge interrupted by a rea d (with or without auto precharge) a read to bank m will interrupt a write on bank n when registered, with the data - out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr be - gins when the read to bank m is registered. the l ast valid write to bank n will be da - ta - in registered one clock prior to the read to bank m (see figure 39 (page 65)). write with auto precharge interrupted by a write (with or without auto precharge) a write to bank m will in terrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (see figure 40 (page 65)).
AS4C32M16SM confidential 54 | p a g e r e v 1 . 0 , j u l y 2014 figure 33: read with auto precharge interrupted by a read
AS4C32M16SM confidential 55 | p a g e r e v 1 . 0 , j u l y 2014 figure 34: read with auto precharge interrupted by a write
AS4C32M16SM confidential 56 | p a g e r e v 1 . 0 , j u l y 2014 figure 35: read with auto precharge
AS4C32M16SM confidential 57 | p a g e r e v 1 . 0 , j u l y 2014 figure 36: read without auto prech arge
AS4C32M16SM confidential 58 | p a g e r e v 1 . 0 , j u l y 2014 figure 37: single read with auto precharge
AS4C32M16SM confidential 59 | p a g e r e v 1 . 0 , j u l y 2014 figure 38: single read without auto precharge
AS4C32M16SM confidential 60 | p a g e r e v 1 . 0 , j u l y 2014 figure 39: write with auto precharge interrupted by a read figure 40: write with auto precharge interrupted by a write
AS4C32M16SM confidential 61 | p a g e r e v 1 . 0 , j u l y 2014 figure 41: write wi th auto precharge
AS4C32M16SM confidential 62 | p a g e r e v 1 . 0 , j u l y 2014 figure 42: write without auto precharge
AS4C32M16SM confidential 63 | p a g e r e v 1 . 0 , j u l y 2014 figure 43: single write with auto precharge
AS4C32M16SM confidential 64 | p a g e r e v 1 . 0 , j u l y 2014 figure 44: single write without auto precharge
AS4C32M16SM confidential 65 | p a g e r e v 1 . 0 , j u l y 2014 auto refresh operation the auto refresh command is used during normal operation of the device to refresh the contents of the array. this command is nonpersistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command sho uld not be issued until the minimum t rp is met following the precharge command. addressing is generated by the internal refresh controller. this makes the address bits dont care during an au - to refresh command. after the auto refresh command is initiat ed, it must not be interrupted by any executable command until t rfc has been met. during t rfc time, command inhibit or nop commands must be issued on each positive edge of the clock. the sdram re - quires that every row be refreshed each t ref period. providi ng a distributed auto re - fresh command calculated by dividing the refresh period ( t ref) by the number of rows to be refreshed meets the timing requirement and ensures that each row is refreshed. alternatively, to satisfy the refresh requirement a burst ref resh can be employed after every t ref period by issuing consecutive auto refresh commands for the number of rows to be refreshed at the minimum cycle rate ( t rfc).
AS4C32M16SM confidential 66 | p a g e r e v 1 . 0 , j u l y 2014 figure 45: auto refresh mode
AS4C32M16SM confidential 67 | p a g e r e v 1 . 0 , j u l y 2014 self refresh operation the self - refresh mode can be use d to retain data in the device, even when the rest of the system is powered down. when in self refresh mode, the device retains data without external clocking. the self refresh command is initiated like an auto refresh command, except cke is disabled (low) . after the self refresh command is registered, all the inputs to the device become dont care with the exception of cke, which must remain low. after self - refresh mode is engaged, the device provides its own internal clocking, enabling it to perform it s own auto refresh cycles. the device must remain in self re - fresh mode for a minimum period equal to t ras and remains in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first , clk must be stable prior to cke going back high. (stable clock is defined as a signal cycling within timing constraints specified for the clock ball.) after cke is high, the device must have nop commands issued for a minimum of two clocks for t xsr becaus e time is required for the completion of any internal refresh in progress. upon exiting the self - refresh mode, auto refresh commands must be issued according to the distributed refresh rate ( t ref/refresh row count) as both self refresh and auto refresh ut ilize the row refresh counter.
AS4C32M16SM confidential 68 | p a g e r e v 1 . 0 , j u l y 2014 figure 46: self refresh mode
AS4C32M16SM confidential 69 | p a g e r e v 1 . 0 , j u l y 2014 power - down power - down occurs if cke is registered low coincident with a nop or command in - hibit when no accesses are in progress. if power - down occurs when all banks are idle, this mode is referred to as precharge power - down; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down. entering power - down deactivates the input and output buffers, excluding cke, for maximum power savings while in standby. the device cannot remain in the power - down state longer than the refresh period (64ms) because no refresh operations are performed in this mode. the power - down state is exited by registering a nop or command inhibit with cke high at the desir ed clock edge (meeting t cks). figure 47: power - down mode
AS4C32M16SM confidential 70 | p a g e r e v 1 . 0 , j u l y 2014 clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, freezing the sync hronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input balls when an internal clock edge is suspended will be ignored; any data present on the d q balls re - mains driven; and burst counters are not incremented, as long as the clock is suspended. exit clock suspend mode by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. figure 48: cl ock suspend during write burst
AS4C32M16SM confidential 71 | p a g e r e v 1 . 0 , j u l y 2014 figure 49: clock suspend during read burst
AS4C32M16SM confidential 72 | p a g e r e v 1 . 0 , j u l y 2014 figure 50: clock suspend mode
AS4C32M16SM confidential 73 | p a g e r e v 1 . 0 , j u l y 2014 this data sheet contains minimum and maximum limits specified over the power supp ly and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some - times occur alliance memory inc . 551 taylor way, san carlos, ca 940 70 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice.

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